`timescale 1ns / 1ps

module RAM_1Kx16_tb;

    reg [9:0] Addr;
    reg Rst;
    reg RE;
    reg WE;
    reg CS;
    reg CLK;
    reg [15:0] Data_in;
    wire [15:0] Data_out;

    RAM_1Kx16 uut (
        .Data_out(Data_out), 
        .Addr(Addr), 
        .Rst(Rst), 
        .RE(RE), 
        .WE(WE), 
        .CS(CS), 
        .CLK(CLK), 
        .Data_in(Data_in)
    );

    initial begin
        CLK = 0;
        forever #5 CLK = ~CLK; // 100MHz
    end

    initial begin
        Rst = 1; RE = 0; WE = 0; CS = 1; Addr = 0; Data_in = 0;
        #20;
        Rst = 0; 
        #10 RE = 1; Addr = 8'hA0;
        #10 RE=0;
        #10 WE = 1;Addr = 8'hA0; Data_in = 16'h1234;
        #10 WE = 0; Data_in = 16'h0000;

        #10 RE = 1; Addr = 8'hA0;
        #10 RE = 0;

        #10 WE = 1;Addr = 8'hA1; Data_in = 16'h5678;
        #10 WE = 0; Data_in = 16'h0000;

        #10 RE = 1;Addr = 8'hA1;
        #10 RE = 0;
 
         #10 RE = 1; Addr = 8'hA0;
        #10 RE = 0;
    end


endmodule